1. Technical Field
The present disclosure relates to the integrated memories field. Specifically, the present disclosure relates to a row decoder for an integrated memory device.
2. Description of the Related Art
Different types of semiconductor memory devices have been proposed in the last decades. Just to mention a few, examples of modern memory devices include static and dynamic random access memories (RAM), read only memories (ROM), and electrically erasable programmable read only memories (E2PROM), such as flash and phase-change memories.
The data memorized in these devices is stored into a plurality of memory cells. Typically, the memory cells are arranged in rows and columns so as to form a bi-dimensional matrix. Each column of the matrix is associated with a corresponding column selection line—referred to as bit line—, and each row of the matrix is associated with a corresponding row selection line—referred to as word line. Each bit line is identified by a corresponding column address, while each word line is identified by corresponding row address.
In order to access a memory cell (e.g., for reading the data stored therein or for writing new data thereinto) belonging to a specific column and to a specific row, the bit line associated with said column and the word line associated with said row are selected by a selector circuit. For this purpose, the selector circuit includes a row decoder and a column decoder configured to decode row and column addresses, respectively, and accordingly bias the bit line and the word line identified by said addresses. In some memory architectures, blocks of more than one memory cell are accessed for being read or written simultaneously, i.e., in parallel to each other. Each of said blocks is generally formed by memory cells belonging to a same row; in this case, for accessing a block of memory cells, the selector circuit selects a word line together with a plurality of bit lines.
Known row decoders usually comprise a plurality of row selection units each for the selection of a respective word line. Particularly, each row selection unit is configured to selectively bias the respective word line to a selection voltage in response to the reception of the specific address which identifies said word line. For this purpose, the row selection units are suitably connected to an address bus formed by a plurality of lines each for providing a specific bit of the row address; for example, each line may convey a respective logic signal, whose value determines the value of a corresponding bit forming the row address. A row selection unit is selectively activated when the combination of the bit values provided by the address bus forms the row address which identifies the word line associated with said row selection unit.
However, this particular arrangement is affected by a serious drawback capable of hindering the correct progress of a reading or a writing operation.
After the selection of a specific word line identified by a specific row address and the completion of a reading or writing operation on addressed memory cells corresponding to said word line, the row address conveyed by the address bus is switched, e.g., for performing a further operation on memory cells corresponding to a different word line. During the transition from the previous row address to the one corresponding to the new word line, the logic signals carried by the lines of the address bus may switch their values at different instants. This may be due to different reasons, such as an asynchronous management of the addresses, or the different propagation delay amounts affecting each logic signal carried by the various lines. Consequently, before said signals have assumed their correct values, the row address carried by the address bus temporarily assumes an unpredicted value, which may trigger the selection of a wrong word line. This drawback may negatively affect the correct progress of the memory device operations, e.g., causing loss of data when a writing operation is performed on memory cells corresponding to a wrong word line.